The present invention relates to a test device for testing an integrated electronic chip including first processor means, said test device including interface means for interfacing said first processor means with other circuits, and second processor means coupled to said first processor means.
Such a test device is generally known in the art as an emulator. Therein the first processor means are replaced by the second processor means which are for instance more performant than the first ones or include a different software programme. The purpose of this test device is to check the behaviour of the other circuits together with these second processor means.
When the electronic chip is for instance only constituted by the first processor means, the socket wherein this chip is plugged may be considered as the interface means and to replace these first processor means by the second processor means this chip is removed from the socket and replaced therein by a connector linked to the second processor means.
In this way the test may be executed with the second processor means running at their normal processing speed. This allows to detect errors appearing only at that processing speed. Moreover, the test is performed by using the same environment, i.e. the other circuits, as when the first procesor means are operating. Thus this test allows detecting errors which do not appear when it is performed in a specific test environment, e.g. when specific test vectors are applied to the interface means instead of using the running second processor means. Indeed, in the case of using test vectors it is almost impossible to provide all the situations which may occur when the processor means are running in their real environment.
Due to the evolution of technology the size of the processor means is now so small that one or more of the above mentioned other circuits may also be integrated on the same chip. As a result it becomes difficult to have access to the interface means, now constituted by "pins" of the first processor means, since these pins are not accessible at the outside of the chip.
A solution to this problem of access would be to connect all these pins to the easily accessible external terminals of the chip. However, this solution is to be rejected because of the then required large number of external terminals and connections between the first processor means and these external terminals.